FIG. 1 illustrates one possible multimedia system. Video data passes from camera 1, through video decoder and interface 2, through DMA (direct memory access) controller 3, through bus 4, and to memory block 5. Audio data passes from microphone 6, through audio decoder and interface 7, through two channel DMA controller 3, through bus 4 and to memory block 5. A processor 8 may, for example, processes the data stored in memory block 5. Camera 1 and video decoder and interface 2 together may be considered to comprise an I/O device 1A. Similarly, microphone 6 and audio decoder and interface 7 may be considered to comprise an I/O device 6A.
Consider an example in which audio data is to be passed from audio decoder and interface 7 to DMA controller 3. Audio decoder and interface 7 issues a DMA request signal to DMA controller 3 via DMA request line 9. When the DMA controller 3 is able to receive data from the audio decoder and interface 7, DMA controller 3 returns a DMA acknowledge signal on DMA acknowledge line 10. The audio decoder and interface 7 then transfers data over data lines 11. Assume that the DMA controller receives and latches eight consecutive words of data from data lines 11. The amount of data in the transfer may be appropriate for this channel which is used for audio data.
Consider further the example in which one frame of video data is to be passed from video decoder and interface 2 to DMA controller 3. Video decoder and interface 2 issues a DMA request signal to DMA controller 3 via DMA request line 12. When the DMA controller 3 is able to receive data from the video decoder and interface 2, DMA controller 3 returns a DMA acknowledge signal on DMA acknowledge line 13. The video decoder and interface 2 then transfers eight consecutive words of data over data lines 14 to DMA controller 3.
The video data path may, however, have higher bandwidth requirements than the audio data path. In the event that the video decoder and interface 2 still has additional data to pass to DMA controller 3, the video decoder and interface 2 issues another DMA request, waits for the DMA controller 3 to return another DMA acknowledge, and then transfers additional data to the DMA controller 3. Numerous time-consuming DMA request/DMA acknowledge sequences are therefore necessary to transfer the desired amount of data. A DMA controller is desired wherein a DMA channel can transfer either large amounts of data or small amounts of data to and/or from I/O devices, neither type of transfer involving a multiple DMA request/DMA acknowledge sequence.